AR0141CS datasheet(4/48 Pages) ONSEMI

4 / 48 page

AR0141CS

www.onsemi.com

Figure 2. Typical Configuration: Serial Four−Lane HiSPi Interface

VAA_PIX

VAA

VDD_PLL

VDD

VDD_IO

From Controller

Master Clock

(6 − 50 MHz)

Digital

I/O

Power1

Digital

Core

Power1

PLL

Power1

Analog

Power1

SDATA

SADDR

SCLK

TRIGGER

OE_BAR

RESET_BAR

TEST

SLVS0_P

SLVS1_P

SLVS0_N

Analog

Power1

DGND

AGND

Digital

Ground

Analog

Ground

VAA VAA_PIX

VDD_PLL

VDD_IO VDD

EXTCLK

To Controller

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.

3. The parallel interface output pads can be left unconnected if the serial output interface is used.

4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as

close as possible to the pad. Actual values and results may vary depending on layout and design considerations.

Check the AR0141CS demo headboard schematics for circuit recommendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital

power planes is minimized.

6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

HiSPi

Power1

SLVS1_N

SLVS2_N

SLVS2_P

SLVS3_P

SLVSC_P

SLVS3_N

SLVSC_N

VDD_SLVS

FLASH

SHUTTER

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