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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9220 데이터시트(PDF) 27 Page - Microchip Technology |
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LAN9220 데이터시트(HTML) 27 Page - Microchip Technology |
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27 / 142 page  2006-2017 Microchip Technology Inc. DS00002417A-page 27 LAN9220 Data path operations for the various supported endianess and word swap configurations are illustrated in Figure 3-9. Table 3-8, "Endian Ordering Logic Operation" illustrates the byte ordering applied by the endian logic for each type of host access. This figure and table assume an internal byte ordering of 3-2-1-0, where ‘3’ is the most significant byte (data[31:24]) and ‘0’ is the least significant byte (data[7:0]). FIGURE 3-8: LAN9220 HOST DATA PATH DIAGRAM "W ORD S W AP" Logic FIFO Port Endian O rdering Logic RX /TX Data FIFO Port A ccess (addresses 00h to 3C h) D irect FIFO A ccess E ndian O rdering Logic RX/TX Data FIFO Direct A ccess (FIFO _SE L = 1) CSRs and S tatus FIFO s FPO R TEN D (H W _C FG [29]) FSELEN D (H W _C FG [28]) D[15:0] (H ost D ata B us) W O RD_S W AP |
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