LAN9220 datasheet(41/142 Pages) MICROCHIP

41 / 142 page

 2006-2017 Microchip Technology Inc.

DS00002417A-page 41

LAN9220

the Burst length regardless of the actual packet length. When configured to do so, the LAN9220 will accept extra data

at the end of the packet and will remove the extra padding before transmitting the packet. The LAN9220 automatically

removes data up to the boundary specified in the Buffer End Alignment field specified in each TX command.

The host can instruct the LAN9220 to issue an interrupt when the buffer has been fully loaded into the TX FIFO con-

tained in the LAN9220 and transmitted. This feature is enabled through the TX command ‘Interrupt on Completion’ field.

Upon completion of transmission, irrespective of success or failure, the status of the transmission is written to the TX

status FIFO. TX status is available to the host and may be read using PIO operations. An interrupt can be optionally

enabled by the host to indicate the availability of a programmable number TX status DWORDS.

Before writing the TX command and payload data to the TX FIFO, the host must check the available TX FIFO space by

performing a PIO read of the TX_FIFO_INF register. The host must ensure that it does not overfill the TX FIFO or the

TX Error (TXE) flag will be asserted.

The host proceeds to write the TX command by first writing TX command ‘A’, then TX command ‘B’. After writing the

command, the host can then move the payload data into the TX FIFO. TX status DWORD’s are stored in the TX status

FIFO to be read by the host at a later time upon completion of the data transmission onto the wire.

FIGURE 3-19:

SIMPLIFIED HOST TX FLOW DIAGRAM

Idle

Check

available

FIFO

space

init

Write

Command

Write

Buffer

Last Buffer in

Packet

Not Last Buffer

Write

Start

Padding

(optional)

Read TX

Status

(optional)

TX Status

Available

LAN9220 데이터시트(PDF) 41 Page - Microchip Technology