Document Number: 001-87220 Rev. *J

Page 16 of 43

Datasheet

Note

It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifi-

Figure 13. 40-pin QFN Example

Figure 14. 28-SSOP Example

Regulated External Supply

In this mode, the PSoC 4100 is powered by an external power

supply that must be within the range of 1.71 V to 1.89 V (1.8

±5%); note that this range needs to include power supply ripple

too. In this mode, VCCD, VDDA, and VDDD pins are all shorted

together and bypassed. The internal regulator is disabled in

firmware.

0.1 µF C4

C5 1 µF

QFN

(Top View)

10

30

29

28

27

26

25

24

23

22

21

2

3

4

5

6

7

8

9

(GPIO) P2[1]

(GPIO) P2[3]

(GPIO) P2[4]

(GPIO) P2[5]

(GPIO) P2[6]

(GPIO) P2[7]

VSS

(GPIO) P4[3]

(GPIO) P0[0]

(GPIO) P0[1]

(GPIO) P0[2]

(GPIO) P0[3]

(GPIO) P0[4]

(GPIO) P0[5]

(GPIO) P0[6]

(GPIO) P0[7]

XRES

1

(GPIO) P3[0]

(GPIO) P2[0]

(GPIO) P2[2]

VSS

VSS

VSS

VSS

VSS

C3 1µF

1µF C1

C2 0.1 µF

(GPIO) P3[0]

( GPIO) P0[1]

SSOP

( Top View)

10

11

P1[2]

28

27

26

25

23

22

21

20

19

18

17

2

3

4

5

6

7

8

9

(GPIO)P1[1]

(GPIO )

(GPIO) P1[7]

( GPIO) P2[2]

(GPIO ) P2[3]

(GPIO ) P2[4]

(GPIO) P2[5]

(GPIO) 2[6]

(GPIO) P4[3]

(GPIO) P0[0]

( GPIO) P0[2]

( GPIO) P0[3]

( GPIO) P0[6]

(GPIO) P0[7]

XRES

VDDD

VSS

1

12

13

14

(GPIO )P1[0]

(GPIO)P3[1]

(GPIO)P3[2]

(GPIO )P3[3]

(GPIO)P2[7]

(GPIO)P4[2]

VCCD

(GPIO)P4[1]

(GPIO)P4[0]

16

15

24

C3 1µF

VSS

VSS

0.1 µF C2

C1 1µF

VSS

P