DLPC3470 datasheet(24/70 Pages) TI1

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PCLK

tp_su

tp_h

tp_wh

tp_wl

tp_clkper

DLPC3470

DLPS110 – APRIL 2018

www.ti.com

Product Folder Links: DLPC3470

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(1)

The active (capture) edge of PCLK for HSYNC_CS, DATEN_CMD and PDATA(23:0) is software programmable, but defaults to the

rising edge.

(2)

Clock jitter (in ns) should be calculated using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met during clock

jitter.

6.13 Parallel Interface General Timing Requirements

see

(1)

MIN

MAX

UNIT

ƒclock

Clock frequency, PCLK

1.0

150.0

MHz

tp_clkper

Clock period, PCLK

50% reference points

6.66

1000

tp_clkjit

Clock jitter, PCLK

Max ƒclock

see (2)

tp_wh

Pulse duration low, PCLK

50% reference points

2.43

tp_wl

Pulse duration high, PCLK

50% reference points

2.43

tp_su

Setup time – HSYNC_CS, DATEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

50% reference points

0.9

tp_h

Hold time – HSYNC_CS, DATEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

50% reference points

0.9

Transition time – all signals

20% to 80% reference

points

0.2

2.0

Figure 5. Parallel Interface General Timing

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