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DLPC3470 데이터시트(PDF) 47 Page - Texas Instruments |
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DLPC3470 데이터시트(HTML) 47 Page - Texas Instruments |
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47 / 70 page ![]() DMD_LS_RDATA DMD_LS_CLK DMD_LS_WDATA DMD_DEN_ARSTZ DMD_HS_WDATA_B_N DMD_HS_WDATA_B_P DMD_HS_WDATA_C_N DMD_HS_WDATA_C_P 600-MHz sub-LVDS DDR (High Speed) DMD_HS_WDATA_D_N DMD_HS_WDATA_D_P DMD_HS_CLK_N DMD_HS_CLK_P DMD_HS_WDATA_E_N DMD_HS_WDATA_E_P DMD_HS_WDATA_F_N DMD_HS_WDATA_F_P DMD_HS_WDATA_G_N DMD_HS_WDATA_G_P DMD_HS_WDATA_H_N DMD_HS_WDATA_H_P DMD_HS_WDATA_A_N DMD_HS_WDATA_A_P Sub-LVDS-DMD (Example DMD) .2 WVGA 854 × 480 display 120-MHz SDR (Low Speed) DLPC3470 ASIC Leave Open for .2 WVGA DMD Leave Open for .2 WVGA DMD Leave Open for .2 WVGA DMD Leave Open for .2 WVGA DMD 47 DLPC3470 www.ti.com DLPS110 – APRIL 2018 Product Folder Links: DLPC3470 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Figure 29. DLP2010 (.2 WVGA) DMD Interface Example (Mapping Option 1 Shown) 8.3.2.10 DLPC3470 controller System Design Consideration – Application Notes System power regulation: It is acceptable for VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD, but to minimize the AC noise component they should be filtered as recommended in the PCB Layout Guidelines for Internal ASIC PLL Power. |
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