PC7447 datasheet(14/66 Pages) ATMEL

14 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Internal Package Conduction

Resistance

For the exposed-die packaging technology, shown in Table 4 on page 13, the intrinsic

conduction thermal resistance paths are as follows:

•

The die junction-to-case (actually top-of-die since silicon die is exposed) thermal

resistance

•

The die junction-to-ball thermal resistance

Figure 33 on page 58 depicts the primary heat transfer path for a package with an

attached heat sink mounted to a printed-circuit board.

Figure 4. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

Note the internal versus external package resistance.

Heat generated on the active side of the chip is conducted through the silicon, then

through the heat sink attach material (or thermal interface material), and finally to the

heat sink where it is removed by forced-air convection.

Because the silicon thermal resistance is quite small, for a first-order analysis, the tem-

perature drop in the silicon may be neglected. Thus, the thermal interface material and

the heat sink conduction/convective thermal resistances are the dominant terms.

External Resistance

Internal Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Printed-Circuit Board

Radiation

Convection

PC7447 데이터시트(PDF) 14 Page - ATMEL Corporation