PC7410 datasheet(28/54 Pages) ATMEL

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PC7410

2141D–HIREL–02/04

IEEE 1149.1 AC Timing

Specifications

Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

16, Figure 17, Figure 18 and Figure 19.

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK

to the midpoint of the signal in question. The output timings are measured at the pins.

All output timings assume a purely resistive 50

Ω load (see Figure 16). Time-of-flight

delays must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes

only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 16. Alternate AC Test Load for the JTAG Interface

Figure 17. JTAG Clock Input Timing Diagram

Note:

VM = Midpoint Voltage (OVDD/2)

Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)

(1)at Recom-

mended Operating Conditions (see Table 4)

Symbol

Parameter

Min

Max

Unit

fTCLK

TCK frequency of operation

33.3

MHz

TCLK

TCK cycle time

tJHJL

TCK clock pulse width measured at OVDD/2

tJR & tJF

TCK rise and fall times

TRST

(2)

TRST assert time

DVJH

(3)

tIVJH

Input Setup Times:

Boundary-scan data

TMS, TDI

tDXJH

(3)

tIXJH

Input Hold Times:

Boundary-scan data

TMS, TDI

tJLDV

(4)

JLOV

Valid Times:

Boundary-scan data

TDO

JLDZ

(4)(5)

JLOZ

(5)

TCK to output high impedance:

Boundary-scan data

TDO

Z0 = 50

Ω

RL = 50

Ω

OVDD/2

Output

TCLK

tJR

tJF

tJHJL

tTCLK

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