PC7410 datasheet(4/54 Pages) ATMEL

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PC7410

2141D–HIREL–02/04

General Parameters

Table 1 provides a summary of the general parameters of the PC7410.

Note:

1. 3.3V I/O bus not supported for 1.5V core power supply processor version.

Features

This section summarizes features of the PC7410’s implementation of the PowerPC

architecture. Major features of the PC7410 are as follows:

•

Branch Processing Unit

–

Four instructions fetched per clock

–

One branch processed per cycle (plus resolving two speculations)

–

Up to one speculative stream in execution, one additional speculative stream

in fetch

–

512-entry branch history table (BHT) for dynamic prediction

–

64-entry, 4-way set associative branch target instruction cache (BTIC) for

eliminating branch delay slots

•

Dispatch Unit

–

Full hardware detection of dependencies (resolved in the execution units)

–

Dispatch two instructions to eight independent units (system, branch,

load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec

permute, AltiVec ALU)

–

Serialization control (predispatch, postdispatch, execution serialization)

•

Decode

–

Forwarding control

–

Partial instruction decode

•

Completion

–

8-entry completion buffer

–

Instruction tracking and peak completion of two instructions per cycle

Table 1. Device Parameters

Parameter

Description

Technology

0.18 µm CMOS, six-layer metal

Die size

6.32 mm × 8.26 mm (52 mm2)

Transistor count

10.5 million

Logic design

Fully-static

Packages

Surface-mount 360 ceramic ball grid array (CBGA)

Surface mount 360 high coefficient of thermal expansion

ceramic ball grid array (HiTCE)

Surface mount 360-column Ci-CGA Package

Core power supply

1.8V ± 100 mV dc or 1.5V ± 50 mV dc (nominal; see Table 4 for

Recommended Operating Conditions)

I/O power supply

1.8V ± 100 mV dc or

2.5V ± 100 mV

3.3V ± 165 mV (603 bus only) (1)

(input thresholds are configuration pin selectable) or

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