CDCM1802RGTT datasheet(5/22 Pages) TI

5 / 22 page

CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†

VDD

Supply voltage

−0.3 V to 3.8 V

Input voltage

−0.2 V to (VDD +0.2 V)

Output voltage

−0.2 V to (VDD +0.2 V)

Yn, Yn, IOSD

Differential short circuit current

Continuous

ESD

Electrostatic discharge (HBM 1.5 kΩ, 100 pF)

>2000 V

Moisture level 16-pin QFN package (solder reflow temperature of 235°C) MSL

Tstg

Storage temperature

−65°C to 150°C

Maximum junction temperature

125°C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

TYP

MAX

UNIT

Supply voltage, VDD

3.3

3.6

Supply voltage, VDD (only functionality)

2.375

3.6

Operating free-air temperature, TA

−40

°C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVPECL INPUT IN, IN

fclk

Input frequency

800

MHz

VCM

High-level input common mode

VDD−0.3

VIN

Input voltage swing between IN and IN,

See Note 1

500

1300

VIN

Input voltage swing between IN and IN,

See Note 2

150

1300

IIN

Input current

VI = VDD or 0 V

±10

µA

RIN

Input impedance

300

kΩ

Input capacitance at IN, IN

LVPECL OUTPUT DRIVER Y0, Y0

fclk

Output frequency, See Figure 4

800

MHz

VOH

High-level output voltage

Termination with 50 Ω to VDD−2 V

VDD−1.18

VDD–0.81

VOL

Low-level output voltage

Termination with 50 Ω to VDD−2 V

VDD−1.98

VDD–1.55

Output voltage swing between Y and Y,

See Figure 4

Termination with 50 Ω to VDD−2 V

500

IOZL

Output 3-state

VDD = 3.6 V, VO = 0 V

µA

IOZH

Output 3-state

VDD = 3.6 V, VO = VDD – 0.8 V

µA

tr/tf

Rise and fall time

20% to 80% of VOUTPP, see Figure 9

200

350

tDuty

Output duty cycle distortion, See Note 3

Crossing point-to-crossing point distortion

−50

tsk(pp)

Part-to-part skew

Any Y0, See Note A in Figure 8

Output capacitance

VO = VDD or GND

LOAD

Expected output load

Ω

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