CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

12

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

LVCMOS

10 pF

Y1

CDCM1802

1 kΩ

1 kΩ

Figure 10. LVCMOS Output Loading During Device Test

LVPECL

Y0, Y0

CDCM1802

50 Ω

Figure 11. LVPECL Output Loading During Device Test

PCB design for thermal functionality

It is recommended to take special care of the PCB design for good thermal flow from the QFN−16 pin package

to the PCB. The current consumption of the CDCM1802 is fixed. JEDEC JESD51−7 specifies thermal

conductivity for standard PCB boards.

Modeling the CDCM1802 with a 4−layer JEDEC board (including four thermal vias) results into 37.5_C max

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications.