CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

10

POST OFFICE BOX 655303

control input characteristics over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Setup time, S0, S1, and EN pin before clock IN

25

ns

Hold time, S0, S1, and EN pin after clock IN

0

ns

Time between latching the EN low transition and when all

outputs are disabled (how much time is required until the

outputs turn off)

10

ns

Time between latching the EN low-to-high transition and

when outputs are enabled based on control settings (how

much time passes before the outputs carry valid signals)

1

µs

Rpullup

Internal pullup resistor on S0, S1, and EN input

42

60

78

kΩ

Three level input high, S0, S1, and EN pin, see Note 1

V

Three level input MID, S0, S1, and EN pin

V

Three level low, S0, S1, and EN pin

V

Input current, S0, S1, and EN pin

−5

µA

Input current, S0, S1, and EN pin

38

85

µA

bias voltage VBB over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VBB

Output reference voltage

V

I − Load − mA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

−5

0

5

101520

253035

vs

LOAD

Figure 7