ML9092-01TB datasheet(48/66 Pages) OKI

48 / 66 page

FEDL9092-01

OKI Semiconductor

ML9092-01/02/03/04

48/66

(7) D1, D0 (DTY1, DTY0) (Display duty select bits)

These bits select the display duty. The correspondence between each bit and display duty is shown in the chart

below. These bits are reset to “0” if the

RESET pin is pulled to a “L” level.

DTY1

DTY0

Display duty

1/8

1/9

1/10

• Control register 2 (FCR2)

STB

DISP

(1) D1 (STB) (Standby mode select bit)

This bit is used to control the standby and normal modes. (Applies to ML9092-03/04.)

1: Standby mode

0: Normal mode

This bit is reset to “0” if the

RESET pin is pulled to a “L” level.

The LSI internal status and pin status during standby mode are as follows:

- RAM data is retained.

- Common output and segment output are VSS level.

- Electronic volume values are retained.

- Port output A is at a “L” level (applies to ML9092-03/04). The status before standby is maintained for port

output B (applies to ML9092-04).

- RC oscillation is stopped. (Oscillation is started with key input, maintained while the KREQ output is at a “H”

level, and stopped when all key switches are turned off and the KREQ output is at a “L” level.)

- Rotary encoder input signals (A and B) are ignored.

- Key input allowed.

- The microcontroller interface (CS, CP, DI/O, KREQ) is operable. (However, only with a KREQ signal from the

key scan, will the KREQ pin output a “H” level.)

- VHIN and VO should be set to VSS or the floating status.

Note: When there is a key input in a standby state, this IC will start oscillating and KREQ output will go to a “H”

level. Execute key scan reading periodically during this “H” level period. Also, execute key scan reading when

the KREQ signal changes from a “H” to “L” level.

(2) D0 (DISP) (Display ON/OFF mode bit)

1: Display ON mode

0: Display OFF mode

This bit selects whether the display is ON or OFF. Writing a “1” to this bit selects the display ON mode. Writing

a “0” to this bit selects the display OFF mode. At this time, the COM and SEG pins will be at the VSS level. Even

if this bit is set to “0”, the display RAM contents will not change. If the

RESET pin is pulled to a “L” level, this

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