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SSM3515CCBZ-R7 데이터시트(PDF) 20 Page - Analog Devices

부품명 SSM3515CCBZ-R7
상세설명  Audio Amplifier
PDF  41 Pages
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SSM3515
Data Sheet
Rev. A| Page 20 of 41
ADDR PIN SETUP AND CONTROL
The ADDR pin sets the device I2C address. See Table11 for details.
CLOCKING
In 3-wire mode (BCLK, FSYNC, SDATA), a BCLK signal must
be provided to the SSM3515 for correct operation. The BCLK
signal must have a minimum frequencyof 2.048 MHz.The BCLK
signal is used for internal clocking of the device. The BCLK rate
is detected automatically, but the sampling frequency must be
known to the device. The supported BCLK rates at 32 kHz to 48
kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400, and 512 times
the sample rate.
Table 11. Pin Setup List
ADDR Pin
SCL Pin
SDA Pin
Control Mode
7-Bit I2C Address
TDM Slot
Connected to Ground Using a 47 kΩ Resistor
SCL
SDA
I2C
0x14
1
Open (No Connection)
SCL
SDA
I2C
0x15
2
Connected to 1.8 V Using a 47 kΩ Resistor
SCL
SDA
I2C
0x16
3
Connected to 1.8 V
SCL
SDA
I2C
0x17
4



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