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AXP288D 데이터시트(PDF) 96 Page - Shenzhen X-Powers Technology Co ., Ltd

부품명 AXP288D
상세설명  PMIC Optimized For Multi-Core High-Performance System
PDF  110 Pages
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AXP288D 데이터시트(HTML) 96 Page - Shenzhen X-Powers Technology Co ., Ltd

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AXP288
PMIC Optimized For Multi-Core High-Performance System
AXP288 Datasheet V1.06
Copyright © 2014 X-Powers Limited. All Rights Reserved.
96
7-6
When BUCK2 controlled by SLP_S0IX_B, the power down sequence setting bit1-0
000-100:5 steps
RW
00
5-3
When BUCK3 controlled by SLP_S0IX_B, the power down sequence setting bit2-0
000-100:5 steps
RW
000
2-0
When BUCK1 controlled by SLP_S0IX_B, the power down sequence setting bit2-0
000-100:5 steps
RW
000
REG 9DH: Run time Sleep power down sequence 2
Default：00H
Reset: System reset
Table 10-87
7-5
When BUCK5 controlled by SLP_S0IX_B, the power down sequence setting bit2-0
000-100:5 steps
RW
000
4-2
When FLDO1 controlled by SLP_S0IX_B, the power down sequence setting bit2-0
000-100:5 steps
RW
000
1-0
Reserved
REG 9EH: Power rail mode in Sleep state
Default：00H
Reset: System reset
Table 10-88
Bit
Description
R/W
Default
7-5
Reserved
4
When BUCK2 controlled by SLP_S0IX_B, power state in sleep mode:
0:off
1:Vsleep
RW
0
3
When BUCK3 controlled by SLP_S0IX_B, power state in sleep mode:
0:off
1:Vsleep
RW
0
2
When BUCK1 controlled by SLP_S0IX_B, power state in sleep mode:
0:off
1:Vsleep
RW
0
1
When BUCK5 controlled by SLP_S0IX_B, power state in sleep mode:
0:off
1:Vsleep
RW
0
0
When FLDO1 controlled by SLP_S0IX_B, power state in sleep mode:
0:off
1:Vsleep
RW
0



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