RF64W datasheet(35/76 Pages) HOPE

35 / 76 page

ADVANCED COMMUNICATIONS & SENSING

Page 35 of 76

RF64

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Config.

Registers

Table 14: Data Operation Mode Selection

MCParam_Data_mode

Data Operation Mode

Continuous

Buffered

Packet

Each of these data operation modes is described fully in the following sections.

5.2. Control Block Description

5.2.1. SPI Interface

5.2.1.1. Overview

As illustrated in the Figure 26 below, the RF64

‟s SPI interface consists of two sub blocks:

 SPI Config: used in all data operation modes to read and write the configuration registers which control all the

parameters of the chip (operating mode, bit rate, etc...)

 SPI Data: used in Buffered and Packet mode to write and read data bytes to and from the FIFO. (FIFO

interrupts can be used to manage the FIFO content.)

RF64

Config.

Registers

FIFO

SPI

CONFIG

(slave)

SPI

DATA

(slave)

NSS_CONFIG

MOSI

MISO

SCK

NSS_DATA

NSS_CONFIG

MOSI

MISO SCK

NSS_DATA

µC

(master)

Figure 26: SPI Interface Overview and uC Connections

Both interfaces are configured in slave mode whilst the uC is configured as the master. They have separate

selection pins (NSS_CONFIG and NSS_DATA) but share the remaining pins:



SCK (SPI Clock): clock signal provided by the uC



MOSI (Master Out Slave In): data input signal provided by the uC



MISO (Master In Slave Out): data output signal provided by the RF64

As described below, only one interface can be selected at a time with NSS_CONFIG having the priority:

RF64W 데이터시트(PDF) 35 Page - HOPE Microelectronics CO., Ltd.

RF64W 데이터시트(HTML) 35 Page - HOPE Microelectronics CO., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

데이터시트 다운로드

링크 URL