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4.0 Register Set (Continued)

3-2

RXPQ

Receive Priority

Queue Enable

This 2-bit field is used to enable Receive Priority Queueing. The number of priority

queues is determined by the following encoding:

00 - Disabled (one queue)

01 - Two queues (0,1)

10 - Three queues (0,1,2)

11 - Four queues (0,1,2,3)

Packets are queued to the priority queues based on the VLAN user_priority field in the

VLAN tag. Any packet without a VLAN tag will be assumed to be priority 0.

TXFAIR

Transmit Fairness

Enable

Enables fairness in the transmit priority queueing process. If set, the transmitter will

implement a rotating priority scheme so all queues get fair access. The highest priority for

the current descriptor selection is always one less than the previous priority. If the last

packet was priority 2, then the priority scheme is 1,0,3,2 from highest to lowest. If no

descriptors are available, the fairness algorithm will be reset such that priority 3 is highest

priority. If this bit is not set, then priority queue 3 will always have the highest priority.

TXPQEN

Transmit Priority

Queueing Enable

Enables the transmit priority queueing feature. If this bit is set, the transmit DMA engine

will select between the available priority queues for transmit data. The priority queues can

be enabled individually using the Command Register (CR) TXE and TXPRI bits. If this bit

is not set, then only the lowest priority queue (TXDP) is enabled, and the TXPRI bits have

no function.

DP83821 데이터시트(PDF) 54 Page - National Semiconductor (TI)