CS5541 datasheet(13/26 Pages) CIRRUS

13 / 26 page

CS5541

DS500PP1

2.6 Serial Port

The CS5541 includes a state machine with an 8-bit

command register, which instructs the ADC to per-

form conversions, and a 24-bit conversion data reg-

ister (read only) to store conversion results. Figure

10 illustrates a block diagram of the internal regis-

ters.

After power is applied to the ADC (the ADC in-

cludes a power-on reset circuit) or after the user

transmits the serial port initialization sequence, the

serial port is set to the command mode. The con-

verter stays in this mode until a valid 8-bit com-

mand is received (the first 8 bits into the serial

port). Once a valid 8-bit data mode command is re-

ceived and interpreted by the ADC’s command

continuous conversions are performed. The SDO

pin falls at the end of a conversion and the user may

read the conversion data by providing 32 serial

clocks (SCLKs), as shown in Figure 11 . The first 8

SCLKs are needed to clear the SDO flag and to

read the status flags. During the next 24 SCLKs,

the conversion data is shifted out of the serial port.

To continue performing the conversions, SDI must

be kept low during the status read time. A new

command can be issued any time other than during

the data read. If the command happens to be a pow-

er save command, the serial port goes back to the

command mode. Otherwise, the conversions will

stop in progress and start new conversions based on

the information in the command byte, and the serial

port will remain in the data mode. Section 2.8,

“Command Register Quick Reference”, lists all

valid commands.

2.7 Serial Port Initialization Sequence

To initialize the serial port of the ADC to the com-

mand mode, the user can transmit the serial port

initialization sequence. The port initialization se-

quence involves clocking seven (or more) SYNC1

command bytes (0xFF) followed by one SYNC0

command byte (0xFE). Note that this sequence

places the ADC’s serial port in the command mode

where it waits until a valid command is received.

This sequence does not reset the internal registers

to their default settings. Further note that the se-

quence can be issued at any time and aids signifi-

cantly in initial code development.

Serial

Interface

SDI

SDO

SCLK

Command Register (1 × 8)

Conversion Data Register (1x24)

Figure 10. CS5541 Register Diagram.

1st Command Time

8 SCLKs

SDO

SCLK

SDI

d *

Data Time

24 SCLKs

MSB

LSB

CH OD OF

8 SCLKs to read status

SDI set low while

reading status & data

o *

* t

d, to - Refer to Table 1. for output timing.

Figure 11. Command and Data Word Timing.

CS5541 데이터시트(PDF) 13 Page - Cirrus Logic

CS5541 데이터시트(HTML) 13 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

데이터시트 다운로드

링크 URL