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CS5541 데이터시트(PDF) 16 Page - Cirrus Logic

부품명 CS5541
상세설명  Low-power, High-Voltage, 24-Bit Delta-Sigma ADC
PDF  26 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5541 데이터시트(HTML) 16 Page - Cirrus Logic

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CS5541
16
DS500PP1
2.9.2 One Time Calibration followed by Con-
tinuous Conversions
After the first command instructing the ADC to en-
ter this mode is given, an offset calibration is per-
formed followed by a gain calibration. Then the
first data conversion is performed. Subsequent con-
versions do not include new calibrations. This al-
lows the ADC to provide maximum throughput for
the filter rate selected.
2.9.3 Continuous Conversions with Default
Calibration Coefficients
After the command instructing the ADC to enter
this mode is given, the ADC will utilize the initial-
ized values of the on-chip calibration registers
(Offset = 0, Gain = 1.0) for all conversions. This al-
lows the ADC to provide maximum throughput for
the filter rate selected. This mode is recommended
when the user is performing a system calibration.
2.9.4 Continuous Conversions with Existing
Calibration Coefficients
After the command instructing the ADC to enter
this mode is given, the ADC will use the coeffi-
cients from the previous calibration to calculate
conversions. If no prior calibration has been per-
formed since power-up, the ADC will use the de-
fault calibration coefficients (Offset = 0, Gain = 1).
The ADC performs conversions at the maximum
throughput for the filter rate selected.
2.9.5 Output Word Timing
Table 1 describes the output word timing of the
CS5541. D3-D0 are the last four bits of the com-
mand word issued, as described in Section 2.8.
Both td and to are represented graphically in Figure
11. td represents the amount of time for a conver-
sion to be completed, once a valid command is re-
ceived. to is the time required for all subsequent
conversions, before a new command is received.
“Throughput” is the rate at which those subsequent
conversions are output.
Notes: 26. td can be off by one MCLK cycle if SCLK is asynchronous to MCLK.
27. Throughput calculations assume that MCLK = 32.768 kHz.
D3-D0
td - First Output (cycles)
Note 26
to - Subsequent Outputs (cycles)
Throughput (SPS)
Note 27
0000
7358
4884
6.7093
0001
7358
2442
13.418
001x
2474
2442
13.418
0100
1550
1012
32.379
0101
1550
506
64.759
011x
538
506
64.759
100x
7358
610
53.718
101x
2474
610
53.718
110x
1550
126
260.06
111x
538
126
260.06
Table 1. Filter Output Word Rates



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