MPC852T datasheet(58/80 Pages) FREESCALE

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MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

FEC Electrical Characteristics

Figure 59. MII Transmit Signal Timing Diagram

15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 27 provides information about the MII async inputs signal timing.

Figure 60 shows the MII asynchronous inputs signal timing diagram.

Figure 60. MII Async Inputs Timing Diagram

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 28 provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Table 27. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK period

Table 28. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

—

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

—

M12

MII_MDIO (input) to MII_MDC rising edge setup

—

M13

MII_MDIO (input) to MII_MDC rising edge hold

—

MII_TX_CLK (input)

MII_TXD[3:0] (outputs)

MII_TX_EN

MII_TX_ER

MII_CRS, MII_COL

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