ST92195D datasheet(184/249 Pages) STMICROELECTRONICS

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ST92195C/D - TWO-CHANNEL I2C BUS INTERFACE (I2C)

7.10 TWO-CHANNEL I2C BUS INTERFACE (I2C)

7.10.1 Introduction

The I2C Bus Master/Slave Interface supports up to

2 serial I2C buses used for communication with

various external devices. It meets all of the re-

quirements of the I2C bus specification (except ex-

tended 10-bit addressing compatibility for slave

operation and CBUS compatibility).

7.10.1.1 General Features

– Conversion of internal 8-bit parallel data to/from

external I2C bus serial data

– Realtime interrupt generation and handling

– Software selectable operation one of two I2C

buses

– Software selectable acknowledge bit generation

– Internal general reset

– 8-bit data read/write register

– 8-bit control register,

– 8-bit status register,

– Operates by default in slave mode and is auto-

matically switched to master mode by loading the

‘data write’ register when the bus is idle.

7.10.1.2 Master Operation

– 4-bit Frequency Control register to select 1 of 16

clock frequencies for the SCL line ranging from

20 kHz to 800 kHz derived from a 4MHz crystal

clock

– Compatible with standard 7 or extended 10-bit

address protocol

– Handles stretching of SCL bus clock pulses by

slaves without restrictions

– Bus arbitration with arbitration loss detection in

multimaster environment

– Bus error detection

– Optional push-pull bus drive capability for faster

communication

7.10.1.3 Slave Operation

– 7-bit address register (cannot be assigned a 10-

bit address)

– The first SCL clock pulse in every data byte is

stretched until the MCU has finished processing

the previously received byte

– Bus error detection

– Optional general call detection

– Operates optionally as Bus Monitor without inter-

fering in any way with bus traffic

– Setup time for any first transmitted data bit can

be adjusted

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