ST92195D datasheet(186/249 Pages) STMICROELECTRONICS

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ST92195C/D - TWO-CHANNEL I2C BUS INTERFACE (I2C)

I2C BUS INTERFACE (Cont’d)

7.10.3 Functional Description

Refer to Section 0.1.6 for the bit definitions.

Figure 2 gives the block diagram of the cell.

By default, the I2C interface is in inactive slave

mode, except when it initiates a transmit or receive

sequence.

After the microcontroller power-on reset state, the

I2C interface is in reset state until the CLEAR bit

(I2CCTR register) is reset.

7.10.3.1 Configuring the interface

Before using the I2C interface, configure it as fol-

lows.

If it is to be used in slave mode, write the address

assigned to the interface in the I2COAR register.

If it is to be used in master mode, write the SCL

clock frequency in the I2CFQR register.

Then, select one of the two buses available and

configure the corresponding pins to the alternate

function (refer to the I/O port chapter).

Depending on your application, you may use the

advanced features (see the UNPROC and UNEXP

bits of the I2CSTR2 register) by setting the AFEN

bit of the I2CCTR register.

You may also optionally set the RSRT and STOP

bits of the I2CCTR register.

You can enable the interrupt on stop condition and

the Spike filter by setting the ISCEN and SFEN

bits of the I2CSTR1 register.

If you want to use the monitor feature, then set the

MONITOR bit in the I2CCTR register.

In all cases reset the CLEAR bit of the I2CCTR

Figure 105. I²C interface block diagram

DATA REGISTER (I2CDR)

OWN ADDRESS REGISTER (I2COAR)

FREQUENCY REGISTER (I2CFQR)

STATUS REGISTER 1 (I2CSTR1)

CONTROL REGISTER (I2CCTR)

SDA In

SCL In

INTERRUPT

STATUS REGISTER 2 (I2CSTR2)

CPU Interrupt

CLOCK

START & STOP

SCL 1

SDA 1

SCL 2

SDA 2

GENERATION

UNIT

DETECTION

UNIT

START & STOP

GENERATION

COMPARATOR

ADDRESS

SHIFT DATA

UNIT

BIT TRANSFER

STATE MACHINE

ERROR AND

ARBITRATION

UNIT

Fast Mode Enable

Acknowledge Bit

SDA Out

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