AX58100LT datasheet(49/71 Pages) ASIX

49 / 71 page

AX58100

EtherCAT Slave Controller

4.5.5

ESC PDI SPI Slave Timing

Figure 4-16: Basic MOSI/MISO timing

Symbol

Description

Min

Typ

Max

Units

TSCLK

SCLK frequency

(≤47MHz)

TSEL_to_CLK

First SCLK cycle after SCS_ESC asserted

TCLK_to_SEL

Deassertion of SCS_ESC

after last SCLK cycle

SPI mode 0/2, SPI mode 1/3

with normal data out sample

SPI mode 1/3 with late data out

sample

TCLK/2+ 5

Tread

Only for read access between address/command and first

data byte. Can be ignored if BUSY or Wait State Bytes are

used.

240

Taccess_delay

Delay between SPI accesses

TMOSI_setup

MOSI valid before SCLK edge

TMOSI_hold

MOSI valid after SCLK edge

TSCLK_to_MISO_valid

MISO valid after SCLK edge

10.5

TSCLK_to_MISO_invalid MISO invalid after SCLK edge

TIRQ_delay

Internal delay between AL event and SINT output to

enable correct reading of the interrupt registers.

180

Table 4-11 PDI SPI Slave Timing Table

AX58100LT 데이터시트(PDF) 49 Page - ASIX Electronics Corporation

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