M58LT128GS datasheet(14/98 Pages) STMICROELECTRONICS

14 / 98 page

2 Signal descriptions

M58LT128GST, M58LT128GSB

14/98

2.7

Latch Enable (L)

Latch Enable latches the A0-A22 address bits on its rising edge. The address latch is

transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.

2.8

Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read

operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read

and in write operations.

2.9

Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the

output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at

VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The

WAIT signal is forced deasserted when Output Enable is at VIH.

2.10

VDD Supply Voltage

VDD provides the power supply to the internal core of the memory device. It is the main power

supply for all operations (Read, Program and Erase).

2.10.1 VDDQ Supply Voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered

independently from VDD. VDDQ can be tied to VDD or can use a separate supply.

2.11

VPP Program Supply Voltage

The VPP pin is both a power supply and a write protect pin. The functions are selected by the

voltage range applied to the pin.

When VPP is lower than VPPLK, it is seen as a write protect pin protecting the whole memory

array. Program and erase operations on all blocks are ignored while VPP is Low.

When VPP is Higher than VPP1, the memory reverts to the previous protection state of the

memory array. Program and erase operations can now modify the data in any block (refer to

Table 21: DC Characteristics - Voltages for VPPLK and VPP1 values). VPP is only sampled at the

beginning of a program or erase; a change in its value after the operation has started does not

have any effect and program or erase operations continue.

If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable

until the Program/Erase algorithm is completed.

The VPP pin must not be left floating or unconnected or the device may become unreliable. A

0.1µF capacitor should be connected between the VPP pin and the VSS Ground pin to decouple

the current surges from the power supply. The PCB track widths must be sufficient to carry the

currents required during Unlock Bypass Program, IPP.

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