AM79C930VCW datasheet(100/161 Pages) AMD

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Am79C930

TIR21: CRC32 Correct Byte Count MSB

This register is the CRC32 Correct Byte Count

MSB register.

Bit

Name

Reset Value

Description

7–4

Reserved

–

Reserved. Must be written as a 0. Reads of this bit produce

undefined data.

3–0

C32C[11:8]

–

CRC32 Correct Count. The value in this register indicates the upper

4 bits of the 12-bit byte position when the CRC32 value was last cor-

rect. CRC32 value 001h corresponds to the first byte of the received

message following the Start of Frame Delimiter. If the value in this

the frame header (plus overhead for PHY and MAC headers and

CRC) for frames that employ 32-bit CRC values, then the frame

should be rejected by the MAC firmware. Note that all bytes begin-

ning with the first byte following the Start of Frame Delimiter and in-

cluding the CRC bytes are included in the CRC32 Correct Count

value, but the bytes that are included in the CRC32 calculation are

dependent upon the setting of the PFL bits of TCR3.

TIR22: CRC8 Correct Byte Count LSB

This register is the CRC8 Correct Byte Count

LSB register.

Bit

Name

Reset Value

Description

7–0

C32C[7:0]

–

CRC8 Correct Count. The value in this register indicates the lower 8

bits of the 12-bit byte position when the CRC8 value was last cor-

rect. CRC8 value 001h corresponds to the first byte of the received

message following the Start of Frame Delimiter. If the value in this

the frame header (plus overhead for PHY and MAC headers and

CRC) for frames that employ 8-bit CRC values, then the frame

should be rejected by the MAC firmware. Note that all bytes begin-

ning with the first byte following the Start of Frame Delimiter and in-

cluding the CRC bytes are included in the CRC8 Correct Count

value, but the bytes that are included in the CRC8 calculation are

dependent upon the setting of the PFL bits of TCR3.

TIR23: CRC8 Correct Byte Count MSB

This register is the CRC8 Correct Byte Count

MSB register .

Bit

Name

Reset Value

Description

7–4

Reserved

–

Reserved. Must be written as a 0. Reads of this bit produce

undefined data.

3–0

C8C[11:8]

–

CRC8 Correct Count. The value in this register indicates the upper

4 of the 12-bit byte position when the CRC8 value was last correct.

CRC8 value 001h corresponds to the first byte of the received mes-

sage following the Start of Frame Delimiter. If the value in this regis-

ter (and TIR22) does not match the length value indicated in the

frame header (plus overhead for PHY and MAC headers and CRC)

for frames that employ 8-bit CRC values, then the frame should be

rejected by the MAC firmware. Note that all bytes beginning with the

first byte following the Start of Frame Delimiter and including the

CRC bytes are included in the CRC8 Correct Count value, but the

bytes that are included in the CRC8 calculation are dependent upon

the setting of the PFL bits of TCR3.

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