LPC55S6X datasheet(41/128 Pages) NXP

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LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

41 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.5 Memory Protection Unit (MPU)

The Cortex-M33 includes a Memory Protection Unit (MPU) which can be used to improve

the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to eight regions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

7.6 Nested Vectored Interrupt Controller (NVIC) for Cortex-M33 (CPU0)

The NVIC is an integral part of the Cortex-M33. The tight coupling to the CPU allows for

low interrupt latency and efficient processing of late arriving interrupts.

7.6.1 Features

• Controls system exceptions and peripheral interrupts.

• 60 vectored interrupts.

• Eight programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table using Vector Table Offset Register (VTOR).

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.7 Nested Vectored Interrupt Controller (NVIC) for Cortex-M33 (CPU1)

The NVIC is an integral part of the Cortex-M33. The tight coupling to the CPU allows for

low interrupt latency and efficient processing of late arriving interrupts.

7.7.1 Features

• Controls system exceptions and peripheral interrupts.

• 60 vectored interrupts.

• Four programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table using VTOR.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

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