LPC55S6X datasheet(43/128 Pages) NXP

43 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

43 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.12 Protected Flash Region (PFR)

The protected flash region is available to configure secure boot, debug authentication,

read UUID, store PUF in key store area, and user defined fields available for specific data

storage.

7.13 Memory mapping

7.14 AHB multilayer matrix

The LPC55S6x uses a multi-layer AHB matrix to connect the CPU buses and other bus

masters to peripherals in a flexible manner that optimizes performance by allowing

peripherals that are on different slave ports of the matrix to be accessed simultaneously

by different bus masters. The device block diagram in Figure 3 shows details of the

available matrix connections.

7.15 Memory Protection Unit (MPU)

CPU0 has a memory protection unit (MPU) that provides fine grain memory control,

enabling applications to implement security privilege levels, separating code, data and

stack on a task-by-task basis. Such requirements are critical in many embedded

applications.

The MPU register interface is located on the CPU private peripheral bus and is described

in detail in Ref 1 “Cortex-M33 DEBUG”

7.16 TrustZone and system mapping on this device

The implementation of ARM TrustZone for CPU0 involves using address bit 28 to divide

the address space into potential secure and non-secure regions. Address bit 28 is not

decoded in memory access hardware, so each physical location appears in two places on

whatever bus they are located on. Other hardware determines which kinds of accesses

(including non-secure callable) are actually allowed for any particular address.

Table 5 shows the overall mapping of the code and data buses for secure and non-secure

accesses to various device resources.

Remark: Address regions considered secure by TrustZone may also be accessible to

CPU1 if it is assigned as a secure master and marked as secure by checker hardware.

Remark: In the peripheral description chapters of this manual, only the native

(non-secure) base address is noted, secure base addresses can be found in this chapter

or created by setting bit 28 in the address as needed.

Table 5.

TrustZone and system general mapping

Start address End address TrustZone, CPU0 only CPU bus CM-33 usage (both CPUs)

0x0000 0000

0x0FFF FFFF Non-secure

Code

Flash memory, Boot ROM, SRAM X.

0x1000 0000

0x1FFF FFFF Secure

Code

Same as above.

0x2000 0000

0x2FFF FFFF Non-secure

Data

SRAM 0, SRAM 1, SRAM 2, SRAM 3, SRAM 4.

0x3000 0000

0x3FFF FFFF Secure

Data

Same as above.

0x4000 0000

0x4FFF FFFF Non-secure

Data

AHB and APB peripherals.

0x5000 0000

0x5FFF FFFF Secure

Data

Same as above.

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