UPD360 datasheet(34/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 34

 2016-2017 Microchip Technology Inc.

7.7

Reset Operation

The following chip-level resets are supported by the device:

• Power-On-Reset (POR)

• Pin Reset (RESET_N)

• Software Reset (SRESET in Hardware Control Register (HW_CTL))

• Watchdog Timer (WDT_STS)

Chip-level resets trigger the sampling of the CFG_SEL0 and CFG_SEL1 configuration straps (see Section 9.8.1, "Con-

figuration Selection," on page 81 for additional information). Chip-level reset completion can be determined by assertion

of the RDY_INT bit in the Interrupt Enable Register (INT_EN) and assertion of the IRQ_N pin.

The following is s summary of steps that occur after a chip-level reset.

System level reset event (POR, RESET_N, SRESET, WDT_STS) occurs.

The device enables the 20 KHz Keep Alive Oscillator, 48 MHz Relaxation Oscillator, and 1MHz Ring Oscillator.

The device samples the CFG_SELx pins.

The device configures itself in accordance with the CFG_SELx pin and settings.

The device is enabled, the RDY_INT bit in the Interrupt Enable Register (INT_EN) asserts, the IRQ_N pin

asserts.

The device disables the 48 MHz Relaxation Oscillator and the Ring Oscillator.

7.8

Clocks and Power Management Registers

This section details the clocks and power management registers. For an overview of the entire device register map, refer

to Section 4.0, "Register Map," on page 19.

7.8.1

CLOCK CONTROL REGISTER (CLK_CTL)

Note 7-1

This bit will always appear asserted when read by software, as the 48 MHz Relaxation Oscillator must

be enabled to facilitate I2C/SPI transactions.

TABLE 7-1:

CLOCKS AND POWER MANAGEMENT REGISTERS MAP

Address

1000h

Clock Control Register (CLK_CTL)

1001h – 13FFh

Reserved for future expansion

Note:

RESERVED address space must not be written under any circumstances. Failure to heed this warn-

ing may result in untoward operation and unexpected results.

Address:

1000h

Size:

8 bits

Bits

Description

Type

Default

7:3

RESERVED

Ring Oscillator Enable

0: Oscillator is disabled.

1: Oscillator is enabled.

R/W

48 MHz Relaxation Oscillator Enable

0: Oscillator is disabled.

1: Oscillator is enabled.

R/W

Note 7-1

20 KHz Keep Alive Oscillator Enable

0: Oscillator is disabled.

1: Oscillator is enabled.

R/W

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