UPD360 datasheet(94/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 94

 2016-2017 Microchip Technology Inc.

9.12.13

DEBUG INTERRUPT ENABLE REGISTER (DBG_ENT_EN)

9.12.14

MATCH DEBOUNCE REGISTER (MATCH_DEB)

9.12.15

PD DEBOUNCE REGISTER (PD_DEB)

Address:

0816h

Size:

8 bits

Bits

Description

Type

Default

7:4

RESERVED

Debug Interrupt Enable 3

When “0”, prevents generation of the respective interrupt.

This bit only exists in standalone DFP mode and is otherwise reserved.

R/W

2:0

Debug Interrupt Enable [2:0]

When “0”, prevents generation of the respective interrupt.

R/W

Address:

0817h

Size:

8 bits

Bits

Description

Type

Default

7:0

Match Debounce

Defines the debounce period utilized before updating the CCx Match Regis-

ters (CCx_MATCH) when not operating in standalone mode.

The units of this register is determined by MATCH_DB_UNITS bit in CC

Hardware Control Register (CC_HW_CTL). When this bit is clear, the units

are 1.6 ms. When this bit is set, the units are 100 us.

Note:

This register must not be modified while the CC debouncer is

enabled.

Note:

The actual debounce time may be +/-1 from the cycle time pro-

grammed.

Note:

The value programmed in this CSR should be at least equal to the

number of thresholds enabled in CCx Sample Enable Registers

(CCx_SAMP_EN). This is only an issue when MATCH_DB_UNITS

is set to 1b.

R/W

Address:

0818h

Size:

8 bits

Bits

Description

Type

Default

7:0

PD Debounce (PD_DEB)

Period used for implementing tPdDebounce.

Note:

This register must not be modified while the CC debouncer is

enabled.

Note:

This register has units of 1 ms.

R/W

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