UPD360 datasheet(112/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 112

 2016-2017 Microchip Technology Inc.

11.1.1.1.2

Buffer Mode

This mode is selected when the EN_FMQ bit in the TX Control Register A (TX_CTL_A) is cleared (default after POR).

In this mode, software writes data into the TX Queue as if it were writing to registers at different addresses. The offset

address range is 1800h-1849h and the buffer has 74 locations.

Only byte access should be used while accessing the TX Queue in this mode. Note that buffer offset address 1800h

contains the least-significant-byte (LSB) (byte that goes out first). Buffer offset address 0x049 has the most-significant-

byte (MSB) (byte that goes out last).

Software can arbitrarily write or read any location in the buffer. Only one packet can be queued into the TX Queue at

one time. Queuing of multiple packets is not supported.

11.1.1.2

TX Queue Data and Processing Modes

The data placed in the TX Queue depends on the selected processing mode. Two modes are supported: “Auto Mode

Data Processing” (AMDP) and “Raw Mode Data Processing” (RMDP).

11.1.1.2.1

Auto Mode Data Processing (AMDP)

This mode is selected by clearing the EN_RMDP bit in the TX Control Register A (TX_CTL_A). In this mode, only the

message data (header and data objects) to be transmitted is queued in the TX Queue. Further, the data is queued as

bytes. Since there is no framing information with the data, the TX Packet Length Register (TX_PKT_LEN) is used to

provide information about the length of message data. Hardware uses this information to determine when and where to

append the CRC. Packet framing (preamble, SOP, and EOP) is automatically inserted by the hardware.

11.1.1.2.2

Raw Mode Data Processing (RMDP)

This mode is selected by setting the EN_RMDP bit in the TX Control Register A (TX_CTL_A). In this mode, software is

responsible for constructing the entire packet including framing, except the preamble and CRC. Since framing involves

K-codes, the data placed in the queue is coded with control information. The data in each byte of the queue is treated

as a “nibble” of packet data that either needs to be 5b encoded by hardware or a K-codes that should be transmitted

without any 5b encoding. There are also some special control bytes to control insertion of CRC and termination of

packet.

When tx_queue_data[5] is “0” then tx_queue_data[3:0] is treated as 4b regular data. This 4b data goes through the

CRC32 generator for CRC calculation and is encoded to 5b per Table 5-1 of USB PD Specification R1.0 (Table 11-1

shows the 4b5b encoding).

When tx_queue_data[5] is “1” then tx_queue_data[4:0] is treated as 5b K-code (see Table 11-1). This data is eliminated

from the CRC calculation and does not go through any further encoding prior to transmission.

The tx_queue_data[7:0] values of 8'hFF and 8'hFE have special meaning. 8'hFF implies that the packet data is done

and hardware should now insert the calculated CRC32 (TX_INS_CRC). 8'hFE implies that the transmission should be

stopped immediately (TX_STOP).

Note that in RMDP, software can compute its own CRC and place it in the Queue as encoded data. In this case, the

TX_INS_CRC code would not be added to the Queue and instead software would proceed with adding the EOP and

terminating the transfer with TX_STOP.

Table 11-1 shows how the byte wide queued data is interpreted or encoded by the transmission logic in raw mode.

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