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UPD360 데이터시트(PDF) 129 Page - Microchip Technology |
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UPD360 데이터시트(HTML) 129 Page - Microchip Technology |
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129 / 221 page ![]() 2016-2017 Microchip Technology Inc. DS00002084C-page 129 UPD360 11.4.1 PD MAC TX REGISTERS The following sub-sections describe the various registers associated with the PD MAC TX logic. 11.4.1.1 TX Control Register A (TX_CTL_A) Address: 1A00h Size: 8 bits Bits Description Type Default 7 RESERVED RO - 6 RETRY_ON_LINE_BUSY Normally hardware will abort a TX packet (including all retry attempts) if the line is Busy when hardware attempts to transmit the packet. (Note that trans- mission of GoodCRC ACK in response for Soft Reset is an exception to this, see the DIS_SPCL_SR_GCRC_ACK bit.) Setting this bit will force hardware to not completely abort the transmission, but rather it will retry the packet up to N_RETRY_CNT times. Failure after N_RETRY_CNT times results in TX_FAILED status in the TX Interrupt Status Register (TX_IRQ_STAT) rather than a TX_ABORTED status. The following conditions will still abort the TX packet: • Hard reset received • Cable reset received (if enabled and the SOP type of the pending TX is SOP', or SOP'', SOP'_Debug or SOP''_Debug) • Good, non-duplicate, non-Ping, non-GoodCRC packet (including soft- reset) received with RX and TX SOP types matching or RX SOP type equaling SOP with TX SOP type not equaling SOP (can be disabled) • Software sets the ABORT bit in the TX Control Register B (TX_CTL_B). R/W 0b 5 DIS_SOP_ABRTS_NON_SOP Normally, when a SOP packet is received, a pending non-SOP packet (includ- ing wait for a GoodCRC) will be aborted. When this bit is set, a non-SOP packet will only be aborted by a packet with the same non-SOP type. R/W 0b 4 DIS_SPCL_SR_GCRC_ACK Disable special treatment of GoodCRC ACK in response to Soft Reset. By default, in auto-response mode a line busy condition will not abort Good- CRC ACK transmission in response to Soft Reset reception. Setting this bit will disable this behavior and instead GoodCRC ACK transmission for Soft Reset will be processed the same as GoodCRC ACK for other packets. Note: When this bit is set, the WAIT4LINE_IDLE bit will affect GoodCRC ACK for Soft Reset as well. R/W 0b |
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