UPD360 datasheet(149/221 Pages) MICROCHIP

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DS00002084C-page 149

UPD360

11.4.2.15

RX FIFO Read Pointer Register (RX_FIFO_RD_PTR)

This register contains the RX FIFO read pointer. Software may update this register to flush a packet based on the known

packet length and starting point.

Software must keep the RX FIFO Read Pointer Control Bits Register coherent with this register if software were to

update this register.

In order to maintain coherency, writes to this register are held in a temporary register and are transferred to the actual

11.4.2.16

RX FIFO Read Pointer Control Bits Register (RX_FIFO_RD_PTR_CTL_BITS)

This register contains the auxiliary control bits of the RX FIFO read pointer.

Software must keep these bits coherent with the RX FIFO Read Pointer if software were to update the latter.

Address:

1A50h

Size:

8 bits

Bits

Description

Type

Default

RESERVED

6:0

RX_FIFO_RD_PTR

This field contains the RX FIFO read pointer.

R/W

0000000b

Address:

1A51h

Size:

8 bits

Bits

Description

Type

Default

RX_FIFO_EMPTY

This field indicates that the RX FIFO is empty (RX FIFO Write Head Pointer

equals the RX FIFO Read Pointer.)

6:2

RESERVED

RX_FIFO_RD_PTR_AT_TOP

This field indicates that the RX FIFO read pointer is at the top of the RAM

(location 127).

RX_FIFO_RX_PTR_WRAP

This field toggles each time the RX FIFO read pointer wraps past the top of

the RAM (location 127). If software updates the RX FIFO read pointer such

that it wraps, this bit must be toggled.

R/W

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