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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD360 데이터시트(PDF) 166 Page - Microchip Technology |
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UPD360 데이터시트(HTML) 166 Page - Microchip Technology |
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166 / 221 page  UPD360 DS00002084C-page 166 2016-2017 Microchip Technology Inc. 11.4.4.9 BMC RX Squelch Assert Time Register (BMC_RX_SQL_ASSERT_TIME) The value of this register is used by the BMC decoder to determine when there is a valid signal. If three edges of the receive signal are seen within this time, then the “squelch” goes active. This time should take into account the minimum bit rate but does not need to account for the duty cycle distortion of the received signal. 11.4.4.10 BMC RX Squelch Hold Time Register (BMC_RX_SQL_HOLD_TIME) The value of this register is used by the BMC decoder to provide time for the CDR circuit to output the final bit of data. A typical hold time would be 1 maximum half bit time pulse desired tolerance. Address: 1AA8h Size: 8 bits Bits Description Type Default 7:0 BMC_RX_SQL_ASSERT_TIME Time in clock cycles x 4 at minimum bit-rate. assert time uS = (BMC_RX_SQL_ASSERT_TIME x 4 + 1) / clock_freq MHz A typical assert time would be 3 maximum half bit times plus desired toler- ance. Note: A value of 70 (decimal) is recommended for this field. R/W 00h Address: 1AA9h Size: 8 bits Note: The Squelch Drop time is based on the BMC RX Maximum High and Low Time registers. Bits Description Type Default 7:0 BMC_RX_SQL_HOLD_TIME Time in clock cycles x 4 at minimum bit-rate. hold time uS = (BMC_RX_SQL_HOLD_TIME x 4 + 1) / clock_freq MHz typical value = ((1 / 2) * ((clock_freq_KHz / min_bit_rate_Kbps) * (100 + tolerance) / 100) - 1) / 4 Note: A value of 23 (decimal) is recommended for this field. R/W 00h |
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