W5200 datasheet(41/88 Pages) WIZNET

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Sn_RX_WR (Socket n RX Write Pointer Register)[R/W][(0x402A + 0x0n00) – (0x402B +

0x0n00)][0x0000]

This register offers the location information to write the receive data. When reading this

0x462A, 0x472A) first and lower bytes (0x402B, 0x412B, 0x422B, 0x432B, 0x442B, 0x452B,

0x462B, 0x472B) later to get the correct value.

Ex) In case of 2048(0x0800) in S0_RX_WR,

0x402A

0x402B

0x08

0x00

Sn_IMR (Socket n Interrupt Mask Register)[R/W][0x402C+0x0n00][0xFF]

It configures the interrupt of Socket n so as to notify to the host. Interrupt mask bit of Sn_IMR

corresponds to interrupt bit of Sn_IR. If interrupt occurs in any SOCKET and the bit is set as ‘1’,

its corresponding bit of Sn_IR is set as ‘1’. When the bits of Sn_IMR and Sn_IR are ‘1’, IR(n)

becomes ‘1’. At this time, if IMR(n) is ‘1’, the interrupt is issued to the host. (‘INTn’ signal is

asserted low)

PRECV

PFAIL

PNEXT

SEND_OK

TIMEOUT

RECV

DISCON

CON

Bit

Symbol

Description

PRECV

Sn_IR(PRECV) Interrupt Mask

Valid only in case of ‘SOCKET = 0’ & ‘S0_MR(P3:P0) = S0_MR_PPPoE’

PFAIL

Sn_IR(PFAIL) Interrupt Mask

Valid only in case of ‘SOCKET = 0’ & ‘S0_MR(P3:P0) = S0_MR_PPPoE’

PNEXT

Sn_IR(PNEXT) Interrupt Mask

Valid only in case of ‘SOCKET = 0’ & ‘S0_MR(P3:P0) = S0_MR_PPPoE’

SENDOK

Sn_IR(SENDOK) Interrupt Mask

TIMEOUT

Sn_IR(TIMEOUT) Interrupt Mask

RECV

Sn_IR(RECV) Interrupt Mask

DISCON

Sn_IR(DISCON) Interrupt Mask

CON

Sn_IR(CON) Interrupt Mask

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