ATXMEGA8E5 datasheet(26/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 26

ATxmega32E5/16E5/8E5

11. System Clock and Clock options

11.1 Features



Fast start-up time



Safe run-time clock switching



Internal Oscillators:



32MHz run-time calibrated and tuneable oscillator



8MHz calibrated oscillator with 2MHz output option and fast start-up



32.768kHz calibrated oscillator



32kHz Ultra Low Power (ULP) oscillator with 1kHz output



External clock options



0.4 - 16MHz Crystal Oscillator



32kHz crystal oscillator with digital correction



External clock input in selectable pin location



PLL with 20 - 128MHz output frequency



Internal and external clock options and 1 to 31x multiplication



Lock detector



Clock Prescalers with 1x to 2048x division



Fast peripheral clocks running at two and four times the CPU clock frequency



Automatic Run-Time Calibration of the 32MHz internal oscillator



External oscillator and PLL lock failure detection with optional non maskable interrupt

11.2 Overview

AVR XMEGA E5 devices have a flexible clock system supporting a large number of clock sources. It incorporates both

accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop

(PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is avail-

able, and can be used for automatic run-time calibration of the 32MHz internal oscillator to remove frequency drift over

voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch to the

internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will

always start up running from the 2MHz output of the 8MHz internal oscillator. During normal operation, the system clock

source and prescalers can be changed from software at any time.

Figure 11-1 on page 27 presents the principal clock system in the XMEGA E5 family of devices. Not all of the clocks need

to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduc-

tion registers, as described in “Power Management and Sleep Modes” on page 29.

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