ATXMEGA8E5 datasheet(52/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 52

ATxmega32E5/16E5/8E5

The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates

from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to

achieve a required baud rate. It also supports external clock input in synchronous slave operation.

An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodu-

lation for baud rates up to 115.2Kbps.

One USART can be connected to the XMEGA Custom Logic module (XCL). When used with the XCL, the data length

within an USART/SPI frame can be controlled by the peripheral counter (PEC) within the XCL. This enables configurable

frame length up to 256 bits. In addition, the TxD/RxD data can be encoded/decoded before the signal is fed into the USART

receiver, or after the signal is output from transmitter when the USART is connected to XCL LUT outputs.

When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers,

shift registers, and baud rate generator enabled. The registers are used in both modes, but their functionality differs for

some control settings. Pin control and interrupt generation are identical in both modes.

PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0 and USARTD0, respectively.

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