ATXMEGA8E5 datasheet(15/153 Pages) MICROCHIP

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Data Sheet Complete

DS40002059A-page 15

ATxmega32E5/16E5/8E5

section with separate lock bits for write and read/write protection. The application table section can be used for save storing

of nonvolatile data in the program memory.

7.4

ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a reg-

ister. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose

registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an

immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register

is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic

is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware multiplier sup-

ports signed and unsigned multiplication and fractional format.

7.4.1

Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different

variations of signed and unsigned integer and fractional numbers:

• Multiplication of unsigned integers

• Multiplication of signed integers

• Multiplication of a signed integer with an unsigned integer

• Multiplication of unsigned fractional numbers

• Multiplication of signed fractional numbers

• Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

7.5

Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program

counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole

address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general

data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset,

the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O mem-

ory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR CPU.

7.6

Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruc-

tion. This information can be used for altering program flow in order to perform conditional operations. Note that the status

register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the

need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an inter-

rupt. This must be handled by software.

The status register is accessible in the I/O memory space.

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