JS28F256P30T85 datasheet(71/102 Pages) INTEL

71 / 102 page

1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set,

even after the erase operation is resumed. Unless the Status Register is cleared using the Clear

Status Register command before resuming the erase operation, possible erase errors may be

masked by the command sequence error.

If a block is locked or locked-down during an erase suspend of the same block, the lock status bits

change immediately. However, the erase operation completes when it is resumed. Block lock

operations cannot occur during a program suspend. See Appendix A, “Write State Machine” on

page 78, which shows valid commands during an erase suspend.

13.2

Selectable One-Time Programmable Blocks

Any of four pre-defined areas from the main array (the four 32 KB parameter blocks together as

one and the three adjacent 128 KB main blocks) can be configured as One-Time Programmable

(OTP) so further program and erase operations are not allowed. This option is available for top or

bottom parameter devices.

Please see your local Intel representative for details about the Selectable OTP implementation.

Table 27.

Selectable OTP Block Mapping

Density

Top Parameter Configuration

Bottom Parameter Configuration

256-Mbit

blocks 258:255 (parameters)

blocks 3:0 (parameters)

block 254 (main)

block 4 (main)

block 253 (main)

block 5 (main)

block 252 (main)

block 6 (main)

128-Mbit

blocks 130:127 (parameters)

blocks 3:0 (parameters)

block 126 (main)

block 4 (main)

block 125 (main)

block 5 (main)

block 124 (main)

block 6 (main)

64-Mbit

blocks 66:63 (parameters)

blocks 3:0 (parameters)

block 62 (main)

block 4 (main)

block 61 (main)

block 5 (main)

block 60 (main)

block 6 (main)

Note:

The 512-Mbit and 1-Gbit devices will have multiple Selectable OTP Areas depending on

the number of 256-Mbit dies in the stack and the placement of the parameter blocks.

JS28F256P30T85 데이터시트(PDF) 71 Page - Intel Corporation

JS28F256P30T85 데이터시트(HTML) 71 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL