JS28F256P30T85 datasheet(46/102 Pages) INTEL

46 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

8.0

Power and Reset Specifications

8.1

Power Up and Down

Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If

VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before

applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN.

Power supply transitions should only occur when RST# is low. This protects the device from

accidental programming or erasure during power transitions.

8.2

Reset Specifications

Asserting RST# during a system reset is important with automated program/erase devices because

systems typically expect to read from flash memory when coming out of reset. If a CPU reset

occurs without a flash memory reset, proper CPU initialization may not occur. This is because the

flash memory may be providing status information, instead of array data as expected. Connect

RST# to the same active low reset signal used for CPU initialization.

Also, because the device is disabled when RST# is asserted, it ignores its control inputs during

power-up/down. Invalid bus conditions are masked, providing a level of memory protection.

Num Symbol

Parameter

Min

Max

Unit

Notes

tPLPH

RST# pulse width low

100

1,2,3,4

tPLRH

RST# low to device reset during erase

µs

1,3,4,7

RST# low to device reset during program

1,3,4,7

tVCCPH

VCC Power valid to RST# de-assertion (high)

1,4,5,6

Notes:

These specifications are valid for all device versions (packages and speeds).

The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.

Not applicable if RST# is tied to Vcc.

Sampled, but not 100% tested.

If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.

If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed

VCC until VCC ≥ VCCMIN.

Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.

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