PIC16F913 datasheet(82/272 Pages) MICROCHIP

82 / 272 page

PIC16F917/916/914/913

DS41250E-page 80

Preliminary

4.7.1

FAIL-SAFE CONDITION CLEARING

The

Fail-Safe condition is cleared after a Reset, the

execution of a SLEEP instruction, or a modification of

the SCS bit. While in Fail-Safe condition, the

PIC16F91X uses the internal oscillator as the system

without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the

OSFIF flag can be cleared.

FIGURE 4-9:

FSCM TIMING DIAGRAM

4.7.2

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at

any point after the device has exited a Reset or Sleep

condition and the Oscillator Start-up Timer (OST) has

expired. If the external clock is EC or RC mode,

monitoring will begin immediately following these

events.

For LP, XT or HS mode the external oscillator may

require a start-up time considerably longer than the

FSCM sample clock time, a false clock failure may be

detected (see Figure 4-9). To prevent this, the internal

oscillator is automatically configured as the system

clock and functions until the external clock is stable

(the OST has timed out). This is identical to

Two-Speed

Start-up

mode.

Once

the

external

oscillator is stable, the LFINTOSC returns to its role as

the FSCM source.

TABLE 4-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

OSCFIF

CM Output

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative

frequencies in this example have been chosen for clarity.

(Q)

CM Test

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit (OSCCON<3>) to verify the

oscillator

start-up

and

system

clock

switchover has successfully completed.

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

8Fh

OSCCON

—

IRCF2

IRCF1

IRCF0

OSTS(2)

HTS

LTS

SCS

-110 q000

-110 x000

90h

OSCTUNE

—

TUN4

TUN3

TUN2

TUN1

TUN0

---0 0000

---u uuuu

2007h(1)

CONFIG

CPD

MCLRE PWRTE

WDTE

FOSC2

FOSC1

FOSC0

—

Legend:

= unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note

See Register 16-1 for operation of all Configuration Word bits.

See Register 4-1 for details.

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