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PCF8564A 데이터시트(PDF) 44 Page - NXP Semiconductors

부품명 PCF8564A
상세설명  Tiny Real-Time Clock/calendar with alarm function and I2C-bus
PDF  65 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
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PCF85063A
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 30 March 2018
44 of 65
NXP Semiconductors
PCF85063A
Tiny Real-Time Clock/calendar with alarm function and I2C-bus
[1]
A detailed description of the I2C-bus specification is given in Ref. 16 “UM10204”.
[2]
I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
[4]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
Table 42.
I2C-bus characteristics
VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =60 k; CL = 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH
with an input voltage swing of VSS to VDD[1].
Symbol
Parameter
Conditions
Min
Max
Unit
Cb
capacitive load for
each bus line
-
400
pF
fSCL
SCL clock frequency
[2] 0
400
kHz
tHD;STA
hold time (repeated)
START condition
0.6
-
s
tSU;STA
set-up time for a
repeated START
condition
0.6
-
s
tLOW
LOW period of the
SCL clock
1.3
-
s
tHIGH
HIGH period of the
SCL clock
0.6
-
s
tr
rise time of both SDA
and SCL signals
20
300
ns
tf
fall time of both SDA
and SCL signals
[3][4] 20
 (V
DD /5.5 V)
300
ns
tBUF
bus free time between
a STOP and START
condition
1.3
-
s
tSU;DAT
data set-up time
100
-
ns
tHD;DAT
data hold time
0
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
s
tVD;DAT
data valid time
0
0.9
s
tVD;ACK
data valid
acknowledge time
00.9
s
tSP
pulse width of spikes
that must be
suppressed by the
input filter
050
ns



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