CS4210 datasheet(33/102 Pages) NSC

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The registers of the CS4210 can broadly be divided into

two categories:

OHCI Configuration Registers

National (Vendor) Specific Configuration Registers

Both are memory mapped offsets accessed via Base

Address Registers (BARs) specified in the PCI Configura-

tion Space Header.

The remaining sub-sections of this chapter are as follows:

• A brief discussion on how to access the registers

located in the PCI Configuration Space

• Register Summary

• Detailed bit formats of all registers

4.1

PCI CONFIGURATION SPACE ACCESS

A PCI configuration read or write cycle is accomplished by

writing the bus, function, device, and register number into

the 32-bit index register at 0CF8h, then performing a corre-

sponding PCI configuration read or write of the 32-bit data

0CF8h (PCI_INDEX) is shown in Table 4-1.

The CS4210 provides a configuration space, whose first

40h bytes adhere to the format outlined in Revision 2.1 of

the document entitled, “PCI Local Bus Specification”. This

is a Type 0 header. This configuration space header con-

tains two 32-bit BARs that specify memory space usage.

The first BAR contains the memory address of the OHCI

defined registers. The second BAR contains the memory

address of the National Semiconductor defined registers.

Table 4-1. PCI Index Register (0CF8h)

Configuration

Space Mapping

RSVD

Bus

Number

Device

Number

Function

Number

1 (Enable)

000 000

0000 0000

xxxx x

xxx

xxxx xx

00 (Always)

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