CS4210 datasheet(8/102 Pages) NSC

8 / 102 page

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Revision 1.0

2.0

Signal Definitions

This section defines the signals and external interface of

the CS4210. Figure 2-1 shows the pins organized by their

functional groupings (internal test and electrical pins are

not shown).

2.1

PIN ASSIGNMENT

The tables in this section use several common abbrevia-

tions. Table 2-1 lists the mnemonics and their meanings.

Figure 2-2 on page 9 shows the pin assignment for the

CS4210 with Tables 2-2 and 2-3, on pages 10 and 11, list-

ing the pin assignments sorted by pin number and alpha-

betically by signal name.

Section 2.2 "Signal Descriptions" starting on page 12 pro-

vides a description for each signal within its associated

functional group.

Figure 2-1. Signal Groups

Table 2-1. Pin Type Definitions

Mnemonic

Definition

Input Pin

I/O

Bidirectional Pin

OOutput

t/s

TRI-STATE Signal

VDD

2.5V Core Power Supply

VDDIO

3.3V I/O Power Supply

VSS

Ground Connection

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY#

TRDY#

STOP#

DEVSEL#

IDSEL

DATA[0:7]

CTRL[0:1]

LREQ

SCLK

LPS

LNKON

DIRECT

PHY-Link

Interface

PCI Bus

Interface

Geode™

PERR#

SERR#

PAR

PREQ#

PGNT#

INTA#

RST#

PCLK

PME#

EECLK

EEDATA

CCLKO

CCLKI

CMC

CMCL

I2C

CS4210

Interface

8kHz Reference

Contender

Clock Interface

Master Control

Interface

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