CS4210 datasheet(81/102 Pages) NSC

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4.4.24.3 Async Response Transmit Context Control

The ContextControl Set/Clear registers contain bits that

control options, operational state and status for the DMA

context. Software can set selected bits by writing ones to

the corresponding bits in the ContextControl Set register.

Software can clear selected bits by writing ones to the cor-

responding bits in the ContextControl Clear register. It is

not possible for software to set some bits and clear others

in an atomic operation. A read from either register returns

the same value.

4.4.24.4 Async Response Transmit Command Pointer

Software initializes CommandPtr.descriptorAddress to con-

tain the address of the first descriptor block that the

CS4210 accesses when software enables the context by

setting ContextControl.run. Software also initializes Com-

mandPtr.Z to indicate the number of descriptors in the first

descriptor block. Software only writes to this register when

both ContextControl.run and ContextControl.active are

zero.

Table 4-43. BAR0+Offset 1A0h (Set) and 1A4h (Clear): AsyncRespTxContextControl Register

Bit

Name

Access

Reset

Description

31:16

RSVD

Reserved

run

RSCU

Run: The run bit is set by software to enable descriptor processing for a

context and cleared by software to stop descriptor processing. The CS4210

only clears this bit on a hardware or software reset. See Section 3.3.2.1

"ContextControl.run" on page 21 for details.

14:13

RSVD

Reserved

wake

RSU

Undef

Wake: Software sets this bit to 1 to cause the CS4210 to continue or

resume descriptor processing. The CS4210 clears this bit on every descrip-

tor fetch. See Section 3.3.2.2 "ContextControl.wake" on page 21 for details.

dead

Dead: The CS4210 sets this bit when it encounters a fatal error. The

CS4210 clears this bit when software clears the run bit. See Section 3.3.2.4

"ContextControl.dead" on page 21 for details.

active

Active: The CS4210 sets this bit to 1 when it is processing descriptors. See

Section 3.3.2.3 "ContextControl.active" on page 21 for details.

9:5

RSVD

Reserved

4:0

eventcode

Undef

Event Code: Following an OUTPUT_LAST* command, the received

ack_code or an “evt_” error code is indicated in this field. Possible values

are: ack_complete, ack_pending, ack_busy_X, ack_busy_A, ack_busy_B,

ack_data_error, ack_type_error, evt_tcode_err, evt_missing_ack,

evt_underrun, evt_descriptor_read, evt_data_read, evt_timeout,

evt_flushed, and evt_unknown.

Table 4-44. BAR0+Offset 1ACh: AsyncRespTxCommandPtr Register

Bit

Name

Access

Reset

Description

31:4

descriptorAddress

RWU

Undef

Descriptor Address: Contains the upper 28 bits of the address of a 16-

byte aligned descriptor block. See Section 3.3.2.5 "CommandPtr" on page

22 for details.

3:0

RWU

Undef

ZBit: Indicates the number of contiguous 16-byte aligned blocks at the

address pointed to by descriptorAddress. If Z is 0, it indicates that the

descriptorAddress is not valid.

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