HD404816FS datasheet(96/100 Pages) RENESAS

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HD404818 Series

During Transmit Clock Input

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time

Scyc

SCK

cyc /

subcyc

1, 4

Transmit clock high and low

widths

SCKH,

SCKL

SCK

0.5

Scyc

Transmit clock rise and fall

times

SCKr,

SCKf

SCK

200

Serial output data delay time t

DSO

500

1, 2

Serial input data setup time

SSI

300

Serial input data hold time

HSI

300

Transmit clock completion

detect time

SCKHD

SCK

cyc /

subcyc

1, 2,

3, 4

Notes: 1. See figure 51.

See figure 52.

3. The transmit clock completion detect time is the high level period after 8 pulses of transmit

clocks are input. The serial interrupt request flag is not set if the next transmit clock is input

before the transmit clock completion detect time has passed.

4. t

subcyc is applied when the MCU is in subactive mode.

subcyc = 244.14 µs (for a 32.768-kHz crystal

oscillator).

tCPr

tCPf

VCC – 0.3 V

0.3 V

OSC1

tCPH

tCPL

1/fCP

Figure 48 Oscillator Timing

0.9VCC

0.1VCC

INT0, INT1

tIH

tIL

Figure 49 Interrupt Timing

RESET

tRSTf

tRSTH

0.9VCC

0.1VCC

Figure 50 Reset Timing

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