AD9083BBCZ datasheet(80/93 Pages) AD

80 / 93 page

AD9083

Data Sheet

Rev. 0 | Page 80 of 93

Addr.

Name

Bits

Bit Name

Description

Reset Access

0x31F JTX_CLK_CTRL_REG

[7:4]

RESERVED

Reserved.

0x0

JTX_ASYNC_PCLK_EN

Enable to the Async Conv Clk Divider.

0x1

R/W

JTX_IFX_CLK_EN

Enable to the IFX Clock Divider.

0x1

R/W

JTX_CONV_CLK_EN

Enable to the Conv Clk Divider.

0x1

R/W

JTX_SYNC_PCLK_EN

Enable to the Sync PCLK Divider.

0x1

R/W

0x320 JTX_CLK_CTRL_REG2

[7:4]

RESERVED

Reserved.

0x0

JTX_CONV_CLK_DIV_

OVERRIDE

Override the Async Conv Clk Div Val with the

Regmap Val.

0x0

R/W

JTX_IFX_CLK_DIV_OVERRIDE

Override the Async Conv Clk Div Val with the

Regmap Val.

0x0

R/W

JTX_SYNC_PCLK_DIV_

OVERRIDE

Override the Async Conv Clk Div Val with the

Regmap Val.

0x0

R/W

JTX_ASYNC_PCLK_DIV_

OVERRIDE

Override the Async Conv Clk DivVal with the

Regmap Val.

0x0

R/W

0x321 IFX_CLK_DIV_REG1

[7:0]

IFX_CLK_DIV_VAL[7:0]

JESD IFX Clock Divider Value.

0x4

R/W

0x322 IFX_CLK_DIV_REG2

[7:1]

RESERVED

Reserved.

0x0

IFX_CLK_DIV_VAL[8]

JESD IFX Clock Divider Value.

0x0

R/W

0x323 ASYNC_PCLK_CTRL

TESTMUX_CLK_SEL

Select Testmux_clk[0] as the asynchronous clock. 0x0

R/W

TESTMUX_CLK_EN

Enable Testmux_clk[0] Select.

0x0

R/W

[5:4]

RESERVED

Reserved.

0x0

ASYNC_LANE_DOUT_SEL

Select Asynchronous Lane Data.

0x0

R/W

ASYNC_LINK_PCLK_SEL

Select Asynchronous Link PCLK.

0x0

R/W

ASYNC_LANE_CLK_SEL

Select Asynchronous Lane Clock.

0x0

R/W

ASYNC_IFX_PCLK_SEL

Select Asynchronous IFX PCLK.

0x0

R/W

0x325 JTX_PCLK_DIV_

INTEGER1

[7:0]

JTX_PCLK_DIV_INTEGER[7:0]

Integer Part for PCLK Divider.

0x0

R/W

0x326 JTX_PCLK_DIV_

INTEGER2

[7:1]

RESERVED

Reserved.

0x0

JTX_PCLK_DIV_INTEGER[8]

Integer Part for PCLK Divider.

0x0

R/W

0x327 JTX_PCLK_DIV_FRAC_

NUM

[7:5]

RESERVED

Reserved.

0x0

[4:0]

JTX_PCLK_DIV_FRAC_NUM

Fractional Numerator for PCLK Divider.

0x0

R/W

0x328 JTX_PCLK_DIV_FRAC_

DEN

[7:5]

RESERVED

Reserved.

0x0

[4:0]

JTX_PCLK_DIV_FRAC_DEN

Fractional Denominator for PCLK Divider.

0x0

R/W

0x329 JTX_IFX_PCLK_DIV_

INTEGER1

[7:0]

JTX_IFX_PCLK_DIV_

INTEGER[7:0]

Integer Part for PCLK Divider.

0x0

R/W

0x32A JTX_IFX_PCLK_DIV_

INTEGER2

[7:1]

RESERVED

Reserved.

0x0

JTX_IFX_PCLK_DIV_

INTEGER[8]

Integer Part for PCLK Divider.

0x0

R/W

0x32B JTX_IFX_PCLK_DIV_

FRAC_NUM

[7:5]

RESERVED

Reserved.

0x0

[4:0]

JTX_IFX_PCLK_DIV_FRAC_

NUM

Fractional Numerator for PCLK Divider.

0x0

R/W

0x32C JTX_IFX_PCLK_DIV_

FRAC_DEN

[7:5]

RESERVED

Reserved.

0x0

[4:0]

JTX_IFX_PCLK_DIV_FRAC_

DEN

Fractional Denominator for PCLK Divider.

0x0

R/W

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