 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
AD9083BBCZ 데이터시트(PDF) 12 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9083BBCZ 데이터시트(HTML) 12 Page - Analog Devices |
|
|
12 / 93 page  AD9083 Data Sheet Rev. 0 | Page 12 of 93 TIMING SPECIFICATIONS Table 14. Parameter Description Min Typ Max Unit SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 4 ns tDH Hold time between the data and the rising edge of SCLK 4 ns tCLK Period of the SCLK 10 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 4 ns tLOW Minimum period that SCLK must be in a logic low state 4 ns tACCESS Maximum time delay between falling edge of SCLK and output data valid for a read operation 2 4 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 6 ns CSB SCLK SDIO tS tDH tLOW tDS tHIGH tCLK tACCESS tH A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 A14 R/W DON’T CARE DON’T CARE DON’T CARE DON’T CARE Figure 2. Serial Port Interface Timing Diagram |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
