| 전자부품 데이터시트 검색엔진 |
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AD9083BBCZ 데이터시트(PDF) 88 Page - Analog Devices |
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AD9083BBCZ 데이터시트(HTML) 88 Page - Analog Devices |
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88 / 93 page ![]() AD9083 Data Sheet Rev. 0 | Page 88 of 93 Addr. Name Bits Bit Name Description Reset Access 01010: /10. 01011: /11. 01100: /12. 01101: /13. 01110: /14. 01111: /15. 10000: /16. 10001: /17. 10010: /18. 10011: /19. 10100: /20. 10101: /21. 10110: /22. 10111: /23. 11000: /24. 11001: /25. 11010: /26. 11011: /27. 11100: /28. 11101: /29. 11110: /30. 11111: /31. 0xD4D SYSREF_IGNORE 7 RESERVED Reserved. 0x0 R 6 SPI_SYSREF_IGNORE_START Start ignoring sysrefs. This bit will self clear once count expires. The first posedge of sysref after the start is passed through, thereafter they are masked until ignore count expires. The bit will self-clear once masking is over. 0x0 R/W 5 SPI_SYSREF_IGNORE_ENABLE Master enable for sysref_ignore block. This also acts as a clock gating signal for the FFs in the block. 0x0 R/W [4:1] SPI_SYSREF_IGNORE_COUNT Number of sysrefs to ignore. Value to be programmed is N-1, e.g. 0 will ignore 1 sysref, 0xF will ignore 16 sysrefs. 0x0 R/W 0 SPI_SYSREF_DISABLE Master disable for sysref, asynchronous – can affect duty cycle of sysref edge closest to bit transition. 0x0 R/W G/H Sync Mode Control Registers 0xE20 TRIGGER_DELAY_VAL_0 [7:0] TRIGGER_DELAY Delay in Trigger Pulse in terms of cic_clk cycles. This delay is a common delay for all path. 0x0 R/W 0xE21 TRIGGER_DELAY_VAL_1 [7:0] I_TRIGGER_DELAY Hardware computed value of Delay in Trigger Pulse in terms of cic_clk cycles. This delay is a common delay for all path. 0x0 R 0xE24 G_H_SYNC_MODE_VAL [7:5] RESERVED Reserved. 0x0 R 4 TRIG_NCO_RESET_EN Enable/Disable for NCO Reset Based on G/H Trig. 1-Enables periodic reset of NCO based on G/H Trig. Upon the arrival of G/H Trig NCO resets are periodically generated at the period of "H". 0-Disables NCO reset based on G/H Trig. 0x0 R/W 3 RESERVED Reserved. 0x0 R 2 DELAY_AUTO_INCR Auto Increment Trigger Delay after each trigger out for calibration purpose. 0x0 R/W |
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