AD9546SLASHPCBZ datasheet(90/205 Pages) AD

90 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 90 of 205

tCARRIER

(8 + x) ×

tCARRIER

K × (8 + x) ×

tCARRIER

tGRID

Figure 65. Grid Timing Diagram

DEMODULATOR SYNCHRONIZATION

The demodulators expect modulation events to occur at regular

periodic intervals, tGRID, with tGRID comprising an integer

number of tCARRIER periods (see Figure 65) such that

tGRID = K × (8 + x) × tCARRIER

where:

K is an integer K ≥ 1.

x is an integer with x ≥ 0.

Essentially, the value of x relates to the divide ratio, R, of the

reference divider as follows:

R = 8 + x

The net effect is that the reference divider produces an output

clock of period, tCARRIER × (8 + x). The reference TDC time

stamps the rising edge of each divider output clock cycle with K

time stamps occurring in each tGRID period.

When the demodulator identifies a modulation event within

the carrier signal, it generates a demodulator clock pulse with

timing according to Figure 64. The demodulator clock pulse

synchronizes the reference divider and causes the reference

TDC to tag the associated time stamp (see Figure 62), which

creates a fixed timing relationship between incoming modula-

tion events and the occurrence of tagged time stamps. Specifically,

every Kth time stamp (see Figure 65) is a tagged time stamp.

The demodulator denotes the next rising edge of the carrier

following the modulation event as the base edge. The user can set

the timing of the demodulator clock pulse to occur a predefined

number of tCARRIER periods after the base edge via the 2-bit

unsigned bit field comprising Bits[5:4] in Register M per the

0 (default), 1, 2, or 3, corresponds to the desired synchronization

edge in Figure 64.

The user must program a bit field value other than the default

value of zero (Bits[5:4] = 0 is not supported).

If a modulation event occurs off grid or the modulation rate

changes to a new tGRID period, the demodulator must

resynchronize. The demodulator requires at least three tCARRIER

periods (including the first modulated cycle) to resynchronize

when Bit 6 in Register M per the register legend in Figure 62 is

Logic 0 and at least eight tCARRIER periods when Bit 6 is Logic 1.

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