AT90PWM2 datasheet(76/365 Pages) ATMEL

76 / 365 page

AT90PWM2/3

4317B–AVR–02/05

ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the

internal pull-up switched off to avoid the digital port function from interfering with the

function of the Analog Comparator.

• ADC1/RXD/ICP1/SCK_A – Bit 4

ADC1, Analog to Digital Converter, input channel 1.

RXD, USART Receive Pin. Receive Data (Data input pin for the USART). When the

USART receiver is enabled this pin is configured as an input regardless of the value of

DDRD4. When the USART forces this pin to be an input, a logical one in PORTD4 will

turn on the internal pull-up.

ICP1 – Input Capture Pin1: This pin can act as an input capture pin for Timer/Counter1.

SCK_A: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is

enabled as a slave, this pin is configured as an input regardless of the setting of DDD4.

When the SPI is enabled as a master, the data direction of this pin is controlled by

DDD4. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTD4 bit.

• TXD/OC0A/SS/MOSI_A, Bit 3

TXD, UART Transmit pin. Data output pin for the USART. When the USART Transmitter

is enabled, this pin is configured as an output regardless of the value of DDD3.

OC0A, Output Compare Match A output: This pin can serve as an external output for the

Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDD3

set “one”) to serve this function. The OC0A pin is also the output pin for the PWM mode

SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured

as an input regardless of the setting of DDD3. As a slave, the SPI is activated when this

pin is driven low. When the SPI is enabled as a master, the data direction of this pin is

controlled by DDD3. When the pin is forced to be an input, the pull-up can still be con-

trolled by the PORTD3 bit.

MOSI_A: SPI Master Data output, Slave Data input for SPI channel. When the SPI is

enabled as a slave, this pin is configured as an input regardless of the setting of DDD3

When the SPI is enabled as a master, the data direction of this pin is controlled by

DDD3. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTD3 bit.

• PSCIN2/OC1A/MISO_A, Bit 2

PCSIN2, PSC 2 Digital Input.

OC1A, Output Compare Match A output: This pin can serve as an external output for the

Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2

set “one”) to serve this function. The OC1A pin is also the output pin for the PWM mode

timer function.

MISO_A: Master Data input, Slave Data output pin for SPI channel. When the SPI is

enabled as a master, this pin is configured as an input regardless of the setting of

DDD2. When the SPI is enabled as a slave, the data direction of this pin is controlled by

DDD2. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTD2 bit.

• PSCIN0/CLKO – Bit 1

PCSIN0, PSC 0 Digital Input.

AT90PWM2 데이터시트(PDF) 76 Page - ATMEL Corporation

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